17-08-2020, 05:32 PM
DRAM coreboards were added to the microbee product range to introduce a lower cost disk drive models when the Texas Instruments 4164 DRAMs were released.
Prior, the SRAM based Microbee 56 was the only disk drive model.
These DRAMs didn't require the 3 voltages that the 4116 DRAMS used thus subsequently were much easier to implement. it just needed +5 Volts.
There were two strands to the DRAM coreboard development. One was to use the Texas Instruments 4500 DRAM Controller and the other was to use the Z80's inbuilt DRAM support.
An important difference between the two circuits was that the inbuilt DRAM version relies upon the Z80 to be the system bus master to ensure that the DRAM was refreshed whereas the 4500 based version independently managed the DRAM refresh. It doesn't sound like much of a difference but using the CPU's inbuilt DRAM refresh makes it complicated to have external device masters such as DMA controllers present. This is because there needs to be a way to continue the DRAM refresh cycles seamlessly between bus master transitions. This limitation explains why the RESET key circuit generates an -NMI (Non-Maskable Interrupt) rather than the original reset. Upon a reset the DRAM contents could be lost because the memory refresh cycles would cease until the CPU because active.
The TI 4164 DRAMs aren't immediately Z80 CPU friendly. The Z80 only has a 7 bit refresh address counter and the TI 4164 8 bits. To address this the coreboard uses a 74LS393 to provide the missing refresh address bit.
Other brands of 64K DRAMs do support 7 bit refresh addresses so the extra address bit is not needed.
With the free space left by the DRAM circuit on the PCB, to further reduce the cost of the DRAM system, the previously separate Floppy Disk Controller circuit was placed onboard with an accompanying Serial Communications Controller (SCC) but to do this the original 50 Expansion connector was omitted. If one still needed a 50 Expansion connector, one could be installed on the underside of the base board with an additional PCB with a myriad of modifications. This wasn't a good option at all so when the Alpha Plus baseboard was designed, the 50 way Expansion connector was added. This had the knock on effect of requiring a redesign of the case's rear panel to accommodate the relocated Expansion connector.
To differentiate the DRAM model from the existing SRAM model, the 128K version was released boasting its extra memory capacity at approximately the same price point.
Later came the cheaper 64K CIAB (Chook in a book) and Starnet variants.
The Z80 can only address 64K of memory so a simple page bank selection scheme is implemented. The RAM is addressed as 4 independent 32K banks through an Output port based register.
Upon a Power up or -NMI, the register is reset so that the default memory map of standard 32K ROM machine is presented.
Prior, the SRAM based Microbee 56 was the only disk drive model.
These DRAMs didn't require the 3 voltages that the 4116 DRAMS used thus subsequently were much easier to implement. it just needed +5 Volts.
There were two strands to the DRAM coreboard development. One was to use the Texas Instruments 4500 DRAM Controller and the other was to use the Z80's inbuilt DRAM support.
An important difference between the two circuits was that the inbuilt DRAM version relies upon the Z80 to be the system bus master to ensure that the DRAM was refreshed whereas the 4500 based version independently managed the DRAM refresh. It doesn't sound like much of a difference but using the CPU's inbuilt DRAM refresh makes it complicated to have external device masters such as DMA controllers present. This is because there needs to be a way to continue the DRAM refresh cycles seamlessly between bus master transitions. This limitation explains why the RESET key circuit generates an -NMI (Non-Maskable Interrupt) rather than the original reset. Upon a reset the DRAM contents could be lost because the memory refresh cycles would cease until the CPU because active.
The TI 4164 DRAMs aren't immediately Z80 CPU friendly. The Z80 only has a 7 bit refresh address counter and the TI 4164 8 bits. To address this the coreboard uses a 74LS393 to provide the missing refresh address bit.
Other brands of 64K DRAMs do support 7 bit refresh addresses so the extra address bit is not needed.
With the free space left by the DRAM circuit on the PCB, to further reduce the cost of the DRAM system, the previously separate Floppy Disk Controller circuit was placed onboard with an accompanying Serial Communications Controller (SCC) but to do this the original 50 Expansion connector was omitted. If one still needed a 50 Expansion connector, one could be installed on the underside of the base board with an additional PCB with a myriad of modifications. This wasn't a good option at all so when the Alpha Plus baseboard was designed, the 50 way Expansion connector was added. This had the knock on effect of requiring a redesign of the case's rear panel to accommodate the relocated Expansion connector.
To differentiate the DRAM model from the existing SRAM model, the 128K version was released boasting its extra memory capacity at approximately the same price point.
Later came the cheaper 64K CIAB (Chook in a book) and Starnet variants.
The Z80 can only address 64K of memory so a simple page bank selection scheme is implemented. The RAM is addressed as 4 independent 32K banks through an Output port based register.
Upon a Power up or -NMI, the register is reset so that the default memory map of standard 32K ROM machine is presented.
