What are this Blank Sockets for?

[mjelic]

Hi All,

Just curious, but why are there blank areas on the Core board, both the ROM version and the Premium versions.
What were they intended for? Could they be used today? Possible to add extra ROMs or RAM to our systems?

[ChickenMan]

First pic, the 2 extra rom positions were for some future options. I know of no current use.

Second pic, it was cheaper to use 4 x 8kb 6264 RAM chips to give 32kb than the original board layout that used 16 x 2kb RAM chips.

[mjelic]

Thanks for the reply.
Pic 1. So if you put a ROM in there... Will it be mapped to the memory space somewhere or nah?
Also, what's all the blank chips for in the right hand area?

Pic 2. OK, so you can't use them to expand to 64K or add extra ROMs?

[MbeeTech]

Thanks for the reply.
Pic 1. So if you put a ROM in there... Will it be mapped to the memory space somewhere or nah?
Also, what's all the blank chips for in the right hand area?

You can put other roms in the 2 blank spots - they will be mapped into memory from C000h to FFFFh as
per the table below referencing I/O port 050h :


As ChickenMan mentioned though, these rom positions were never used, so to make use of them 
you would have to write your own code to control the access to them.

The non-populated parts on the right hand side of the board are for the hardware serial port option.
As standard, all microbees have a serial port on the baseboard which uses an I/O port of the PIO
to bit-bash (software timed) serial communications. This limited the baud rate to a maximum of 19k baud
with handshaking enabled, 9600 baud without.  The Coreboard option uses the Zilog SCC and can operate
up to 38k baud in the microbee implementation with a lot less overhead for the processor.  It provided
2 additional serial ports at up to this speed.

Pic 2. OK, so you can't use them to expand to 64K or add extra ROMs?

Correct.  They map to the same location as the 4 x 8k rams.

[mjelic]

Dead set, you never cease to amaze me at the utter depth and complete knowledge of every aspect of the Bee! You are a credit!!

>.jpg Port50Map.JPG (Size: 50.06 KB / Downloads: 4)

When I try to click on that, it gives me an error, saying I don't have permission to get to that page.

[Ernest]

Dead set, you never cease to amaze me at the utter depth and complete knowledge of every aspect of the Bee! You are a credit!!

>.jpg  Port50Map.JPG (Size: 50.06 KB / Downloads: 4)

When I try to click on that, it gives me an error, saying I don't have permission to get to that page.

Hi mjelic,
Try logging out and viewing as a guest without logging in.
There is something strange with how this site works and there a many of us who cant see the linked images when we are logged in.

Ernest

[MbeeTech]

Hopefully you can see the image now, logged in or out.
I changed the post and referenced the picture with a URL instead of adding the picture as an attachment.

Thanks for your kind words.

[mjelic]

Yes I can see it now, thanks.

But does that mean if either of the extra Roms are enabled (bit 2 is set low), does that mean that video ram gets crunchecd by the extra rom, unless you also change Bit 4, to move the video ram to B000h?

[MbeeTech]

But does that mean if either of the extra Roms are enabled (bit 2 is set low), does that mean that video ram gets crunchecd by the extra rom, unless you also change Bit 4, to move the video ram to B000h?

Bit 2 enables ROM 2 if low, ROM 3 if High  (ie, you can't have ROM 2 and ROM 3 in memory at the same time.
ROM 2 or 3, depending on which you select as above, appear in memory at C000h to FFFFh.

As far as I am aware, Video takes precedence, so if video is enabled (bit 3 LOW) for mapping to F000h to FFFFh (bit 4 low)
access to ROM 2 or 3 will only be in the range of C000h to EFFFh.

Likewise, if video is enabled (bit 3 LOW) for mapping to 8000h to 8FFFh (Bit 4 High) the boot rom will only be in the range 9000h to BFFFh
and ROM 2 / ROM 3 will be fully addressable at C000h to FFFFh.

By the way, if you disable the ROMs (bit 2 HIGH) DRAM bank 0, block 1 (the second 32k) appears from 8000h to either EFFFh or FFFFh depending on
whether you have video enabled for F000h to FFFFh (bit 4 LOW) or from 9000h to FFFFh if you have video enabled for 8000h to 8FFFh (bit 4 HIGH).
Of course, if you disable video access altogether, with ROMS disabled, you get full access to DRAM bank 0 block 1 at 8000h to FFFFh.

[Ernest]

Food for thought,
Not all may realise but it is possible, all be it, an under utilization of the DRAM Coreboard, but by replacing ROM 1 with Microworld Basic V5.22 burnt into a 128K EPROM the board will boot up and behave as a standard 32K ROM Basic machine. Add into the ROM2 location, Wordbee or EDASM (or any of the ROMs designated for the C000h - DFFFh PAK location) and you can call this with the PAK command from basic, just as you would in a normal ROM base machine.

For the adventurous, you could even use a 512K EPROM in location of ROM2 and with a little minor track modification and with decoding Port 04 and a latch you could have eight PAK locations that could be easily called from basic with the PAKx command. You could even set up your port decoding and latch in some of the unused real estate that was left for the SCC and associated hardware on the right hand side. Alternately PORT 04 may still be available on X5 pin8 depending on what Mainboard configuration you have, in which case you will just need the latch 4042 or similar as talked about in the FLASH ON ROM MICROBEES topic.

Just a thought
Ernest