18-10-2020, 12:58 PM
Hi All.
I thought I would post a quick update in regards to the Classic Plus kit.
What I have been doing of late it to convert the FPGA logic design from its Altium Schematic based design entry
to ISE (webpack 14.7) schematic design entry.
Although using Altium Designer as the front end for my FPGA work has been good up until now, with a complex design like this that
needs more constraints added, Altium designer just doesn't allow for more than basic clock constraints.
Moving to entry direct into ISE should allow me to get the problems in the logic design sorted and the project moving ahead.
All the best,
I thought I would post a quick update in regards to the Classic Plus kit.
What I have been doing of late it to convert the FPGA logic design from its Altium Schematic based design entry
to ISE (webpack 14.7) schematic design entry.
Although using Altium Designer as the front end for my FPGA work has been good up until now, with a complex design like this that
needs more constraints added, Altium designer just doesn't allow for more than basic clock constraints.
Moving to entry direct into ISE should allow me to get the problems in the logic design sorted and the project moving ahead.
All the best,