31-08-2026, 02:29 PM
On the regular 128k coreboard A2 is not decoded for the FDC chip select, and the chip select covers an 8 address range (0x40 to 0x47), so the ports at 0x44->0x47 are also available at 0x40 -> 0x43.
The side select port is at 0x48 which selects the drive number, side & density. Reads to 0x48 are required to test the DRQ/INT status from the FDC.
As to the CF configuration, I have no idea what ports it uses.
The side select port is at 0x48 which selects the drive number, side & density. Reads to 0x48 are required to test the DRQ/INT status from the FDC.
As to the CF configuration, I have no idea what ports it uses.