18-04-2025, 10:35 AM
Hi Someone
I got the Z80 and the 6845 working off the same clock source, so the Z80 is running at 3.38Mhz (ZCLK) with the standard dot clock of 13.5Mhz, The 6845 clock (CCLK) is half the ZCLK at 1.68Mhz, and this is also used to drive a number of TTL multiplexers so that the CRTC access the Video/Character RAM on the first half of the CCLK and the Z80 accesses it on the second half of CCLK.
However, there is a fundamental difference in how the two devices access memory. The 6845 accesses the video memory on every clock cycle, whereas the Z80 needs between 3 and 5 ZCLK clock cycles to complete a memory read or write - the actual number of clock cycles depends on the instruction being executed. and as 3 (or 5) is not divisible by 2, there needs to be some restrictions on how the Z80 accesses video memory
So the Z80 has access to video memory when CCLK is low and the CRTC has access to video memory when CCLK is high. ZCLK is arranged for the Z80 memory read and write strobe edge to occur when CCLK is low. Video data is extracted from video memory when CCLK is high, and is latched by the LOAD* pulse at the end of the high period of CCLK for subsequent character and video generation.
When the Z80 processor requires access to memory, it generates a ZMEMRQ* signal. If this access is to video memory (bit 15 high), the clock PAL generates a ZWAIT* signal until the next time that CCLK is low. The Z80 processor then completes its memory access. The maximum delay that can occur is one half cycle of CCLK, which is 300 ns.
The end result of this (somewhat complicated) approach is that the Z80 runs at full speed for all access to the program PROM and general purpose RAM, and has a 1 Z80 clock cycle delay for 50% of the access to the Video and Character Generator RAM - this is an acceptable compromise as the Z80 is dedicated to the Video card, and has lots of spare processing power
The advantage of this approach is that video memory can be updated at any time during the CRT scan as Z80 access does not conflict with the CRTC access (and hence there are no display "flashes") without haveing to wait for line or frame flyback
I hope this all makes sense. I have attached a timing diagram that shows the interaction between the DOTC, CCLK and ZCLK.
I got the Z80 and the 6845 working off the same clock source, so the Z80 is running at 3.38Mhz (ZCLK) with the standard dot clock of 13.5Mhz, The 6845 clock (CCLK) is half the ZCLK at 1.68Mhz, and this is also used to drive a number of TTL multiplexers so that the CRTC access the Video/Character RAM on the first half of the CCLK and the Z80 accesses it on the second half of CCLK.
However, there is a fundamental difference in how the two devices access memory. The 6845 accesses the video memory on every clock cycle, whereas the Z80 needs between 3 and 5 ZCLK clock cycles to complete a memory read or write - the actual number of clock cycles depends on the instruction being executed. and as 3 (or 5) is not divisible by 2, there needs to be some restrictions on how the Z80 accesses video memory
So the Z80 has access to video memory when CCLK is low and the CRTC has access to video memory when CCLK is high. ZCLK is arranged for the Z80 memory read and write strobe edge to occur when CCLK is low. Video data is extracted from video memory when CCLK is high, and is latched by the LOAD* pulse at the end of the high period of CCLK for subsequent character and video generation.
When the Z80 processor requires access to memory, it generates a ZMEMRQ* signal. If this access is to video memory (bit 15 high), the clock PAL generates a ZWAIT* signal until the next time that CCLK is low. The Z80 processor then completes its memory access. The maximum delay that can occur is one half cycle of CCLK, which is 300 ns.
The end result of this (somewhat complicated) approach is that the Z80 runs at full speed for all access to the program PROM and general purpose RAM, and has a 1 Z80 clock cycle delay for 50% of the access to the Video and Character Generator RAM - this is an acceptable compromise as the Z80 is dedicated to the Video card, and has lots of spare processing power
The advantage of this approach is that video memory can be updated at any time during the CRT scan as Z80 access does not conflict with the CRTC access (and hence there are no display "flashes") without haveing to wait for line or frame flyback
I hope this all makes sense. I have attached a timing diagram that shows the interaction between the DOTC, CCLK and ZCLK.