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reset key and nmi - fathertedcrilly - 15-10-2026
I'm in the process of building out the PIO module of Novato.
This in turn requires proper interrupt handling in the z80 core instead of stubs
Having a look across posts in various forums and whatever tech manuals are available, it seems that all static RAM models tie the reset key to the reset pin.
Whereas dynamic RAM models tie the reset key to the NMI pin.
Is this a fair assumption ?
Thanks
Tony
RE: reset key and nmi - MbeeTech - 15-10-2026
Hi Tony.
Yes, the RESET key circuit on DRAM based coreboards goes to the NMI pin of the CPU.
The reason for this is that a reset can be performed while not losing DRAM refresh in the process.
Stopping the Z80 via holding RESET low too long, or A BUSREQ/BUSACK cycle that is longer than the
DRAM refresh rate will cause the memory contents to become invalid. Resetting the CPU also clears the
refresh counter.
To work around this, triggering an NMI to do a software reset keeps the refresh counter going and DRAM
being refreshed to keep it's contents valid.
RE: reset key and nmi - fathertedcrilly - 15-10-2026
(15-10-2026, 12:29 PM)MbeeTech Wrote: Hi Tony.
Yes, the RESET key circuit on DRAM based coreboards goes to the NMI pin of the CPU.
The reason for this is that a reset can be performed while not losing DRAM refresh in the process.
Stopping the Z80 via holding RESET low too long, or A BUSREQ/BUSACK cycle that is longer than the
DRAM refresh rate will cause the memory contents to become invalid. Resetting the CPU also clears the
refresh counter.
To work around this, triggering an NMI to do a software reset keeps the refresh counter going and DRAM
being refreshed to keep it's contents valid.
Cheers
When I get to the DRAM models, the reset logic will need to be expanded to cater for this
on a related point, Is it safe to say that interrupts really aren't used anywhere on the standard platform save for this and the PIO B RTC bit ( on the PC85 ) ?
Now back to the grindstone. I forgot to code the EI delay into the core
Thanks
Tony
RE: reset key and nmi - MbeeTech - 15-10-2026
(15-10-2026, 12:54 PM)fathertedcrilly Wrote: Is it safe to say that interrupts really aren't used anywhere on the standard platform save for this and the PIO B RTC bit ( on the PC85 ) ?
Thanks
Tony
The only interrupts that are used are generated by the PIO.
They are :
RTC interrupt (if fitted) or VSYNC (if linked, PC85 for Pseudo RTC),
Serial port receive,
Parallel port for printer RDY/ACK,
and on the 256TC for the keyboard token available.
Other software / hardware may create interrupts of course (eg: RTTY / FAX on the parallel port etc..)
but that's the extent of the interrupt usage for a regular system.
RE: reset key and nmi - fathertedcrilly - 15-10-2026
(15-10-2026, 01:33 PM)MbeeTech Wrote:(15-10-2026, 12:54 PM)fathertedcrilly Wrote: Is it safe to say that interrupts really aren't used anywhere on the standard platform save for this and the PIO B RTC bit ( on the PC85 ) ?
Thanks
Tony
The only interrupts that are used are generated by the PIO.
They are :
RTC interrupt (if fitted) or VSYNC (if linked, PC85 for Pseudo RTC),
Serial port receive,
Parallel port for printer RDY/ACK,
and on the 256TC for the keyboard token available.
Other software / hardware may create interrupts of course (eg: RTTY / FAX on the parallel port etc..)
but that's the extent of the interrupt usage for a regular system.
Hmm I thought the serial and parallel ports were always polled with the standard software suite ?
I suppose things like serial mice might be different
probably not going to bother with the 256TC so I can ignore that
At some point, all these kind of inputs into Novato will be part of the repo's Wiki
Thanks
Tony
RE: reset key and nmi - MbeeTech - 15-10-2026
(15-10-2026, 02:48 PM)fathertedcrilly Wrote: Hmm I thought the serial and parallel ports were always polled with the standard software suite ?
I suppose things like serial mice might be different
probably not going to bother with the 256TC so I can ignore that
At some point, all these kind of inputs into Novato will be part of the repo's Wiki
Thanks
Tony
Certainly with the later versions of the BIOS, the parallel port is interrupt driven.
Not sure about the serial port (if that is selected as a printer output in config/init), but
I know TELCOM uses interrupts for its serial routines for the PIO based serial I/O.
I also know that the serial mouse routines in the xBIOS uses interrupts.
RE: reset key and nmi - fathertedcrilly - 16-10-2026
(15-10-2026, 08:44 PM)MbeeTech Wrote:(15-10-2026, 02:48 PM)fathertedcrilly Wrote: Hmm I thought the serial and parallel ports were always polled with the standard software suite ?
I suppose things like serial mice might be different
probably not going to bother with the 256TC so I can ignore that
At some point, all these kind of inputs into Novato will be part of the repo's Wiki
Thanks
Tony
Certainly with the later versions of the BIOS, the parallel port is interrupt driven.
Not sure about the serial port (if that is selected as a printer output in config/init), but
I know TELCOM uses interrupts for its serial routines for the PIO based serial I/O.
I also know that the serial mouse routines in the xBIOS uses interrupts.
I'm going to build the capability in any case ( as it's the whole point of the exercise )
After all, it's not rocket science
Just have to put the work in
Thanks
Tony